Parallel-pipelined architecture for 2-D ICT VLSI implementation

The Integer Cosine Transform (ICT) has been shown to be an alternative to the DCT for image processing. This paper presents a parallel-pipelined architecture of an 8x8 ICT(10, 9, 6, 2, 3, 1) processor for image compression. The main characteristics of this architecture are: high throughput, low latency, reduced internal storage and 100% efficiency in all computational elements. The processor has been designed in 0.35-?m CMOS technology with an operational frequency of 300MHz.

• Type: Conference
• Year: 2003
• Where: ICIP
• Authors: Juan A. Michell, Gustavo A. Ruiz, Angel M. Buron
• Keywords: 0.35m Cmos Technology, ICIP 2003, Image Compression, Image Processing, Integer Cosine Transform, Low Latency, Operational Frequency