Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs

We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocates applications with optimized buffer requirement and software/hardware implementation cost. At the same time, application performance is guaranteed with sustainable throughput during run-time reconfigurations. As the main contribution, we formulate the constraint based application allocation, scheduling, and reconfiguration analysis, and propose a design Pareto-point calculation flow. A public domain solver - Gecode is used in solutions finding. The capability of our method has been exemplified by two cases studies on applications from media and communication domains.

• Type: Conference
• Year: 2010
• Where: DATE
• Authors: Jun Zhu, Ingo Sander, Axel Jantsch
• Keywords: DATE 2010, Hardware, Optimized Buffer Requirement, Pareto Efficient Design, Reconfigurable Streaming Applications