Pareto Points in SRAM Design Using the Sleepy Stack Approach

Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for SRAM which occupies large transistor count in most state-of-the-art chip designs. We propose a novel ultralow leakage SRAM design which we call “sleepy stack SRAM.” Unlike many other previous approaches, sleepy stack SRAM can retain logic state during sleep mode, which is crucial for a memory element. Compared to the best alternative we could find, a 6-T SRAM cell with highVth transistors, the sleepy stack SRAM cell with 2xVth at 110o C achieves more than 2.77X leakage power reduction at a cost of 16% delay increase and 113% area increase. Alternatively, by widening wordline transistors and transistors in the pull-down network, the sleepy stack SRAM cell can achieves 2.26X leakage reduction without increasing delay at a ...

• Type: Conference
• Year: 2005
• Where: VLSI
• Authors: Jun-Cheol Park, Vincent John Mooney III
• Keywords: Leakage Power, Leakage Power Consumption, Sleepy Stack Sram, VLSI 2005