Performance and power modeling in a multi-programmed multi-core environment

This paper describes a fast, automated technique for accurate on-line estimation of the performance and power consumption of interacting processes in a multi-programmed, multi-core environment. The proposed technique does not require modifying hardware or applications. The performance model uses reuse distance histograms, cache access frequencies, and the relationship between the throughput and cache miss rate of each process to predict throughput. The system-level power model is derived using multi-variable linear regression, accounting for cache contention. Both models are validated on multiple real multi-core systems using SPEC CPU2000 benchmarks; their performance and power estimates are within 3.5% of measured values on average. We explain how to integrate the two models for power estimation during process assignment, helpful for power-aware assignment. Categories and Subject Descriptors C.0 [General]: Modeling of computer architecture General Terms Experimentation Keywords perfo...

• Type: Conference
• Year: 2010
• Where: DAC
• Authors: Xi Chen, Chi Xu, Robert P. Dick, Zhuoqing Morley Mao
• Keywords: Cache Access Frequencies, Cache Miss Rate, Computer Architecture, DAC 2010, System-level Power Model