DAC 2010 - PDF Preprint Papers

DAC 2010 Design Automation Conference

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed DAC-2010 Paper

click to vote

DAC
2010
ACM

399views Computer Architecture» more DAC 2010»

Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms

14 years 4 months ago

Download cadal.cse.nsysu.edu.tw

We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...

Chenjie Yu, Peter Petrov

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	399	Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms	claim
2	342	Cyber-physical systems: the next computing revolution	claim
3	325	Representative path selection for post-silicon timing prediction under variability	claim
4	322	Efficient fault simulation on many-core processors	claim
5	295	Consistent runtime thermal prediction and control through workload phase detection
6	293	Parallel multigrid preconditioning on graphics processing units (GPUs) for robust power grid analysis	claim
7	251	Cost-driven 3D integration with interconnect layers	claim
8	230	Crosstalk noise and bit error rate analysis for optical network-on-chip	claim
9	227	Cost-aware three-dimensional (3D) many-core multiprocessor design	claim
10	224	Cyber-physical energy systems: focus on smart buildings	claim
11	216	Thermal monitoring of real processors: techniques for sensor allocation and full characterization
12	208	A correlation-based design space exploration methodology for multi-processor systems-on-chip	claim
13	208	Xetal-Pro: an ultra-low energy and high throughput SIMD processor	claim
14	203	A probabilistic and energy-efficient scheduling approach for online application in real-time systems	claim
15	200	Theoretical analysis of gate level information flow tracking	claim
16	199	Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation	claim
17	194	A parallel integer programming approach to global routing	claim
18	189	An efficient dual algorithm for vectorless power grid verification under linear current constraints	claim
19	186	Rewiring for robustness	claim
20	185	Eyecharts: constructive benchmarking of gate sizing heuristics	claim
21	183	Coverage in interpolation-based model checking	claim
22	181	Scalable specification mining for verification and diagnosis	claim
23	179	SCEMIT: a systemc error and mutation injection tool	claim
24	178	Non-uniform clock mesh optimization with linear programming buffer insertion	claim
25	177	QuickYield: an efficient global-search based parametric yield estimation with performance constraints	claim
26	176	Network on chip design and optimization using specialized influence models	claim
27	176	Detecting tangled logic structures in VLSI netlists	claim
28	171	Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement	claim
29	170	Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system	claim
30	170	An error tolerance scheme for 3D CMOS imagers	claim
31	169	RAMP gold: an FPGA-based architecture simulator for multiprocessors	claim
32	166	Lattice-based computation of Boolean functions	claim
33	166	An AIG-Based QBF-solver using SAT for preprocessing	claim
34	166	Electronic design automation for social networks	claim
35	166	Automatic multithreaded pipeline synthesis from transactional datapath specifications	claim
36	165	Parallel hierarchical cross entropy optimization for on-chip decap budgeting	claim
37	164	TSV stress aware timing analysis with applications to 3D-IC layout optimization	claim
38	163	LUT-based FPGA technology mapping for reliability	claim
39	163	An efficient algorithm to verify generalized false paths	claim
40	162	PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme	claim
41	162	Processor virtualization and split compilation for heterogeneous multicore embedded systems	claim
42	162	The aethereal network on chip after ten years: goals, evolution, lessons, and future	claim
43	162	Adaptive and autonomous thermal tracking for high performance computing systems	claim
44	162	Virtual channels vs. multiple physical networks: a comparative analysis	claim
45	160	Performance yield-driven task allocation and scheduling for MPSoCs under process variation	claim
46	157	Networks on Chips: from research to products	claim
47	156	Reducing the number of lines in reversible circuits	claim
48	156	Circuit modeling for practical many-core architecture design exploration	claim
49	155	On the costs and benefits of stochasticity in stream processing	claim
50	152	BooM: a decision procedure for boolean matching with abstraction and dynamic learning	claim
51	152	Instruction cache locking using temporal reuse profile	claim
52	152	Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression	claim
53	150	An efficient phase detector connection structure for the skew synchronization system	claim
54	150	MFTI: matrix-format tangential interpolation for modeling multi-port systems	claim
55	143	A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs	claim
56	142	SRAM-based NBTI/PBTI sensor system design	claim
57	141	Post-silicon validation opportunities, challenges and recent advances	claim
58	140	Recovery-driven design: a power minimization methodology for error-tolerant processor modules	claim
59	140	Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips	claim
60	138	Towards scalable system-level reliability analysis	claim
61	138	Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations	claim
62	136	Performance and power modeling in a multi-programmed multi-core environment	claim
63	134	Automated compact dynamical modeling: an enabling tool for analog designers	claim
64	133	Trace-driven optimization of networks-on-chip configurations	claim
65	129	Node addition and removal in the presence of don't cares	claim
66	127	Stochastic computation	claim
67	105	Worst-case response time analysis of resource access models in multi-core systems	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers