The Performance of Cache-Coherent Ring-based Multiprocessors

Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective use of powerful microprocessors in shared memory multiprocessor configurations. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessors, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new microprocessors. In this paper we evaluate the performance of the unidirectional slotted ring interconnection for small to medium scale shared memory systems, using a hybrid methodology of analytical models and trace-driven simulations. We evaluate both snooping and directory-based coherence protocols for the ring and compare it to high performance split transaction buses.

• Type: Conference
• Year: 1993
• Where: ISCA
• Authors: Luiz André Barroso, Michel Dubois
• Keywords: Hardware, ISCA 1993, Memory Multiprocessors, Scale Shared Memory, Shared Memory