A performance counter architecture for computing accurate CPI components

Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaining insight into the behavior of an application on a given microprocessor; consequently, they are widely used by software application developers and computer architects. However, computing CPI stacks on superscalar out-of-order processors is challenging because of various overlaps among execution and miss events (cache misses, TLB misses, and branch mispredictions). This paper shows that meaningful and accurate CPI stacks can be computed for superscalar out-of-order processors. Using interval analysis, a novel method for analyzing out-oforder processor performance, we gain understanding into the performance impact of the various miss events. Based on this understanding, we propose a novel way of architecting hardware performance counters for building accurate CPI stacks. The additional hardware for implementin...

• Type: Conference
• Year: 2006
• Where: ASPLOS
• Authors: Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
• Keywords: Accurate Cpi Stacks, ASPLOS 2006, CPI Stacks, Miss Events, Programming Languages