Performance-impact limited area fill synthesis

Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, area fill features are inserted into the layout to improve uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertion. We then give the first formulation of the Performance Impact Limited Fill (PILFill) problem, and describe three practical solution approaches based on Integer Linear Programming (ILP-I and ILP-II) and the Greedy method. We test our methods on two layout testcases obtained from industry. Compared with the normal fill method,3 our ILP-II method achieves between 25% and 90% reduction in terms of total weighted edge...

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Yu Chen, Puneet Gupta, Andrew B. Kahng
• Keywords: DAC 2003, Design Automation, Impact Limited Fill, Layout Density Control, Local Layout Density