Physical unclonable function and true random number generator: a compact and scalable implementation

Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signatures and volatile secret keys, whereas TRNGs are used for generating random padding bits, initialization vectors and nonces in cryptographic protocols. This paper proposes a scalable design technique to implement both a delay-based PUF and a jitter-based TRNG using ring oscillators. By sharing and reusing a significant amount of hardware resources, we achieve nearly 50% area reduction as compared to discrete implementations. We also propose and demonstrate a co-processor-based design that renders the circuit portable across various embedded processor platforms on FPGAs. Multiple scaled designs using 32 to 128 ring oscillators have been implemented and verified on Xilinx Spartan3S500E FPGA. A representative design uses 32 3-inverter ring oscillators, 64 flipflops/latches, 31 2-input XOR gates and control circu...

• Type: Conference
• Year: 2009
• Where: GLVLSI
• Authors: Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, Patrick Schaumont
• Keywords: 3-inverter Ring Oscillators, GLVLSI 2009, Random Padding Bits, Ring Oscillators, VLSI