Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage

Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause noise margins to decrease, while increasing current and frequency makes supply noise injection larger, especially noise caused by inductance in the supply lines. Creating power distribution systems is one of the key challenges in modern chip design. Decoupling capacitance helps reduce inductance effects, but there is often a peak in the supply impedance that occurs at a resonant frequency caused roughly by the package inductance and the chip decoupling capacitors. This frequency is on the order of 100MHz, which is much lower than the operating frequency of the processor. We propose pipeline damping, an architectural technique which controls instruction issue to guarantee bounds on current variation around the frequency of the supply resonance, thus reducing the resulting supply noise. Damping is a cheaper alt...

• Type: Conference
• Year: 2003
• Where: ISCA
• Authors: Michael D. Powell, T. N. Vijaykumar
• Keywords: Current Variation, Hardware, ISCA 2003, Supply Noise, Supply Voltages