A pipelined clock-delayed domino carry-lookahead adder

Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined for superior speed performance which makes it an attractive option in high-speed logic implementation. This paper presents the design of two different high-speed pipeline configurations of a 32-bit carry look-ahead adder using CD domino gates utilizing efficient clocking methodology to reduce the overall critical path delay. Categories and Subject Descriptors B.2.4 [Arithmetic and Logic Structures]: High-Speed Arithmetic; B.7.1 [Integrated Circuits]: Types and Design Styles—algorithms implemented in hardware, VLSI General Terms Algorithms, Performance, Design Keywords Arithmetic, VLSI, Dynamic Logic

• Type: Conference
• Year: 2003
• Where: GLVLSI
• Authors: Bhushan A. Shinkre, James E. Stine
• Keywords: Dynamic Logic, Dynamic Logic Family, GLVLSI 2003, Non-inverting Logic, VLSI