GLVLSI
2003
IEEE
14 years 8 months ago
2003
IEEE
We introduce a simple hierarchical design technique for using dynamic domino circuits to build high-performance self-timed data path circuits. We wrap the dynamic domino circuit i...
GLVLSI
2003
IEEE
14 years 8 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...