A Portable Framework for High-Speed Parallel Producer/Consumers on Real CMP, SMT and SMP Architectures

This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi-Threading processors (SMT) and Shared Memory Processors (SMP). To build an HSPC, we use a code generation approach in two stages. Stage One generates data structures to eliminate memory interference. This is done by adjusting and timing cache/buffer/stack placements and lengths for an idealized producer/consumer. Perfect load-balancing is achievable for CMP and SMP, but not for SMT due to simultaneousexecution interference. In Stage Two, the codebase is refined inside its target application: profiling events sent from Python to a consumer that computes profiling information. Stage two further tests the impact of altering event sizes, synchronization primitives, container libraries, and processor affinity. Stage two achieves near perfect balancing for CMP and SMP architectures, but SMT still performs poor...

• Type: Conference
• Year: 2007
• Where: IPPS
• Authors: Richard T. Saunders, Clinton L. Jeffery, Derek T. Jones
• Keywords: Current Shared Memory, Distributed And Parallel Computing, IPPS 2007, Shared Memory, Simultaneous Multi-Threading Processors