Power-aware communication optimization for networks-on-chips with voltage scalable links

Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energyefficient static algorithm which optimizes the energy consumption of task communications in NoCs with voltage scalable links. In order to find optimal link speeds, the proposed algorithm (based on a genetic formulation) globally explores the design space of NoCbased systems, including task assignment, tile mapping, routing path allocation, task scheduling and link speed assignment. Experimental results show that the proposed design technique can reduce energy consumption by 28% on average compared with existing techniques. Categories and Subject Descriptors: C.3 [Special-purpose and application-based systems]: Real-time and embedded systems General Terms: Algorithms, Design

• Type: Conference
• Year: 2004
• Where: CODES
• Authors: Dongkun Shin, Jihong Kim
• Keywords: CODES 2004, Energy Consumption, Energyefficient Static Algorithm, Link Speed, Software Engineering