Power Efficient Data Cache Designs

This paper investigates some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in performance. The basic idea is to combine different threshold voltages with different cache organizations that provide different levels of performance. Multi-banked organizations in combination with different approaches to allocate data to cache banks are explored. Some of the resulting cache architectures are shown to provide a good tradeoff between power and performance.

• Type: Conference
• Year: 2003
• Where: ICCD
• Authors: Jaume Abella, Antonio González
• Keywords: Cache Architectures, Cache Energy Consumption, Data Cache Designs, Hardware, ICCD 2003