ICCD 2003 - PDF Preprint Papers

ICCD 2003 International Conference on Computer Design

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ICCD
2003
IEEE

177views Hardware» more ICCD 2003»

SAT-Based Algorithms for Logic Minimization

14 years 8 months ago

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This paper introduces a new method for two-level logic minimization. Unlike previous approaches, the new method uses a SAT solver as an underlying engine. While the overall minimi...

Samir Sapra, Michael Theobald, Edmund M. Clarke

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Id	Views	Title	Status

1	177	SAT-Based Algorithms for Logic Minimization	claim
2	167	Virtual Page Tag Reduction for Low-power TLBs	claim
3	165	CMOS High-Speed I/Os - Present and Future	claim
4	147	Design Flow Enhancements for DNA Arrays
5	147	An Efficient VLIW DSP Architecture for Baseband Processing	claim
6	145	Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities	claim
7	143	Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case	claim
8	143	Aggressive Test Power Reduction Through Test Stimuli Transformation	claim
9	141	Structured ASICs: Opportunities and Challenges	claim
10	140	Reducing Multimedia Decode Power using Feedback Control	claim
11	140	Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems	claim
12	137	Dynamic Thread Resizing for Speculative Multithreaded Processors	claim
13	134	An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk	claim
14	130	On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume	claim
15	129	Reducing dTLB Energy Through Dynamic Resizing	claim
16	127	Structural Detection of Symmetries in Boolean Functions	claim
17	126	Design and Performance of Compressed Interconnects for High Performance Servers	claim
18	123	Simplifying SoC design with the Customizable Control Processor Platform	claim
19	121	Distributed Reorder Buffer Schemes for Low Power	claim
20	121	Interface Synthesis using Memory Mapping for an FPGA Platform	claim
21	115	Reducing Compilation Time Overhead in Compiled Simulators	claim
22	113	Exploiting Microarchitectural Redundancy For Defect Tolerance	claim
23	113	Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity	claim
24	112	Power Efficient Data Cache Designs	claim
25	111	Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files	claim
26	111	Routed Inter-ALU Networks for ILP Scalability and Performance	claim
27	109	Independent Test Sequence Compaction through Integer Programming	claim
28	107	Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches	claim
29	105	Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling	claim
30	104	On Reducing Register Pressure and Energy in Multiple-Banked Register Files	claim
31	104	Non-Crossing OBDDs for Mapping to Regular Circuit Structures	claim
32	98	Specifying and Verifying Systems with Multiple Clocks	claim
33	98	ROAD : An Order-Impervious Optimal Detailed Router for FPGAs	claim
34	89	Precomputation-based Guarding for Dynamic and Leakage Power Reduction	claim
35	89	Power-Time Tradeoff in Test Scheduling for SoCs	claim
36	83	Physical Design of the "2.5D" Stacked System	claim

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