Power Estimation of Cell-Based CMOS Circuits

PPP is a Web-based simulation and synthesis environment for low-power design. In this paper we describe the gate-level simulation engine of PPP, that achieves accuracy always within 6% from SPICE, while keeping performance competitive with traditional gate-level simulation. This is done by using advanced symbolic models of the basic library cells, that exploit the physical understanding of the main powerconsuming phenomena. VERILOG-XL is used as simulation platform to maintain compatibility with design environments. The Web-based interface allows the user to remotely access and execute the simulator using his/her own Webbrowser (without the need of any software installation).

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Alessandro Bogliolo, Luca Benini, Bruno Riccò
• Keywords: Computer Architecture, DAC 1996, Gate-level Simulation, Gate-level Simulation Engine, Traditional Gate-level Simulation