Power-optimal repeater insertion considering Vdd and Vth as design freedoms

This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion lengths, repeater sizes, and Vdd and Vth levels for a net with a delay target, and it reduces more than 50% power over a previous work which does not consider Vdd and Vth optimization. This work further presents the power saving when multiple Vdd and Vth levels are used in repeater insertion at the full-chip level. Compared to the case with single Vdd and Vth suggested by ITRS, optimized dual Vdd and dual Vth reduce overall global interconnect power by 47%, 28% and 13% for 130nm, 90nm and 65nm technology nodes, respectively, but extra Vdd or Vth levels only give marginal improvement. We also show that an optimized single Vth reduce interconnect power almost as effective as dual-Vth does, in contrast to the need of dual Vth for logic circuits. Categories and Subject Descriptors: B.7.2[Hardware]: Integrated ci...

• Type: Conference
• Year: 2005
• Where: ISLPED
• Authors: Yu Ching Chang, King Ho Tam, Lei He
• Keywords: Dual Vth, ISLPED 2005, Repeater Insertion, Vth Levels