Power-Performance Trade-Off of a Dependable Multicore Processor

As deep submicron technologies are advanced, new challenges, such as power consumption and soft errors, are emerging. A naïve technique, which utilizes emerging multicore processors and relies upon thread-level redundancy to detect soft errors, is power hungry. Another technique, which relies upon instruction-level redundancy, diminishes computing performance seriously. This paper investigates trade-off between power and performance of a dependable multicore processor, which is named multiple clustered core processor (MCCP). It is proposed to hybrid thread- and instruction-level redundancy to achieve both large power efficiency and small performance loss. Detailed simulations show that the MCCP exploiting the hybrid technique improves power efficiency in energy-delay product by 13% when it is compared with the one exploiting the naïve thread-level technique.

• Type: Conference
• Year: 2007
• Where: PRDC
• Authors: Toshinori Sato, Toshimasa Funaki
• Keywords: Dependable Computing, Instruction-level Redundancy, Multicore Processor, PRDC 2007, Soft Errors