Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture

This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-uniformly, where some threads may be slowed down significantly, while others are not. This may cause severe performance problems such as sub-optimal throughput, cache thrashing, and thread starvation for threads that fail to occupy sufficient cache space to make good progress. Unfortunately, there is no existing model that allows extensive investigation of the impact of cache sharing. To allow such a study, we propose three performance models that predict the impact of cache sharing on co-scheduled threads. The input to our models is the isolated L2 cache stack distance or circular sequence profile of each thread, which can be easily obtained on-line or off-line. The output of the models is the number of extra L2 cache misses for each thread due to cache sharing. The models differ by their complexity and predi...

• Type: Conference
• Year: 2005
• Where: HPCA
• Authors: Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin
• Keywords: Cache Sharing Impact, Computer Architecture, Extra L2 Cache, HPCA 2005, Isolated L2 Cache