HPCA 2005 - PDF Preprint Papers

HPCA 2005 International Symposium on High-Performance Computer Architecture

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HPCA
2005
IEEE

179views Distributed And Parallel Com...» more HPCA 2005»

Unbounded Transactional Memory

14 years 11 months ago

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Hardware transactional memory should support unbounded transactions: transactions of arbitrary size and duration. We describe a hardware implementation of unbounded transactional ...

C. Scott Ananian, Krste Asanovic, Bradley C. Kuszm...

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Id	Views	Title	Status

1	179	Unbounded Transactional Memory	claim
2	179	SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors	claim
3	170	Tapping ZettaRAMTM for Low-Power Memory Systems	claim
4	168	A Small, Fast and Low-Power Register File by Bit-Partitioning	claim
5	160	Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems	claim
6	154	Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors	claim
7	145	Chip Multithreading: Opportunities and Challenges	claim
8	143	Scatter-Add in Data Parallel Architectures	claim
9	143	Enterprise IT Trends and Implications for Architecture Research	claim
10	138	Improving Multiple-CMP Systems Using Token Coherence	claim
11	137	A Performance Comparison of DRAM Memory System Optimizations for SMT Processors	claim
12	135	Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications	claim
13	133	Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture	claim
14	131	The Soft Error Problem: An Architectural Perspective	claim
15	128	Characterizing and Comparing Prevailing Simulation Techniques	claim
16	124	Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions	claim
17	124	Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors	claim
18	122	A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks	claim
19	121	SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs	claim
20	121	Performance, Energy, and Thermal Considerations for SMT and CMP Architectures	claim
21	120	Multithreaded Value Prediction	claim
22	119	An Efficient Programmable 10 Gigabit Ethernet Network Interface Card	claim
23	115	On the Limits of Leakage Power Reduction in Caches	claim
24	112	Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses	claim
25	110	Power Efficient Processor Architecture and The Cell Processor	claim
26	109	Software Directed Issue Queue Power Reduction	claim
27	104	Microarchitectural Wire Management for Performance and Power in Partitioned Architectures	claim
28	97	Distributing the Frontend for Temperature Reduction	claim
29	97	Heat Stroke: Power-Density-Based Denial of Service in SMT	claim
30	96	Transition Phase Classification and Prediction	claim
31	94	A Unified Compressed Memory Hierarchy	claim
32	89	Checkpointed Early Load Retirement	claim
33	84	Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE	claim

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