A probabilistic analysis of pipelined global interconnect under process variations

— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a novel delay metric named DMA for estimation of interconnect delay probability density function considering process variations. Without considerable loss in accuracy, DMA can achieve high computational efficiency even in a large space of random variables. We then propose a comprehensive probabilistic methodology for sampling transfers, on a shared latch inserted global interconnect, that highly improves the reliability of the interconnect. Improvements up to 125% are observed in the reliability when compared to deterministic sampling approach. It is also shown that dual phase clocking scheme for pipelined global interconnect is able to meet more stringent timing constraints due to its lower latency.

• Type: Conference
• Year: 2006
• Where: ASPDAC
• Authors: Navneeth Kankani, Vineet Agarwal, Janet Meiling Wang
• Keywords: ASPDAC 2006, Global Interconnect, Inserted Global Interconnect, Interconnect Delay Probability