Probabilistic gate-level power estimation using a novel waveform set method

A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each circuit node is estimated. Existing methods have local glitch filtering approaches that fail to model this phenomenon correctly. Glitches originated from a node may be filtered in some, but not necessarily all, of its successor nodes. Our waveform set approach allows us to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For other circuit, experimental results using the ISCAS’85 benchmarks show that the waveform set method generally provides significantly better estimates of the transition density compared to previous techniques. Categories and Subject Descriptors B.6.3 [LOGIC DESIGN]: Design Aids—Switching theory; B.6.1 [LOGIC DESIGN]: Design Styles—Combinational logic General Terms Alg...

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas
• Keywords: GLVLSI 2007, Power Estimation Technique, Probabilistic Power Estimation, Transition Density, VLSI