A Probability-Based Approach to VLSI Circuit Partitioning

Iterative-improvement 2-way min-cut partitioning is an important phase in most circuit partitioning tools. Most iterative improvement techniques for circuit netlists like the Fidducia-Mattheyses (FM) method compute the gains of nodes using local netlist information that is only concerned with the immediate improvement in the cutset. This can lead to misleading gain calculations. Krishnamurthy suggested a lookahead (LA) gain calculation method to ameliorate this situation; however, as we show, it leaves considerable room for improvement. We present here a probabilistic gain computation approach called PROP1 that is capable of capturing the global and future implications of moving a node at the current time. Experimental results show that for the same number of runs, PROP performs much better than FM (by about 30%) and LA (by about 27%), and is also better than many recent state-of-the-art clusteringbased partitioners like EIG1, WINDOW, MELO and PARABOLI by 15% to 57%. We also show that...

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Shantanu Dutt, Wenyong Deng
• Keywords: Computer Architecture, DAC 1996, Gain Calculation, Misleading Gain Calculations, Most Iterative Improvement