Sciweavers

MICRO
2003
IEEE

Processor Acceleration Through Automated Instruction Set Customization

14 years 5 months ago
Processor Acceleration Through Automated Instruction Set Customization
Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded applications. Hardware, in the form of new function units (or co-processors), and the corresponding instructions, are added to a baseline processor to meet the critical computational demands of a target application. The central challenge with this approach is the large degree of human effort required to identify and create the custom hardware units, as well as porting the application to the extended processor. In this paper, we present the design of a system to automate the instruction set customization process. A dataflow graph design space exploration engine efficiently identifies profitable computation subgraphs from which to create custom hardware, without artificially constraining their size or shape. The system also contains a compiler subgraph matching framework that identifies opportunities to explo...
Nathan Clark, Hongtao Zhong, Scott A. Mahlke
Added 05 Jul 2010
Updated 05 Jul 2010
Type Conference
Year 2003
Where MICRO
Authors Nathan Clark, Hongtao Zhong, Scott A. Mahlke
Comments (0)