Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cach

As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to design processors featuring hundreds of general-purpose cores. However, though a large number of cores speeds up parallel code sections, Amdahl’s law requires speeding up sequential sections too. We argue that it will become possible to dedicate a substantial fraction of the chip area and power budget to achieve high sequential performance. Current general-purpose processors contain a handful of cores designed to be continuously active and run in parallel. This leads to power and thermal constraints that limit the core’s performance. We propose removing these constraints with a sequential accelerator (SACC). A SACC consists of several cores designed for ultimate sequential performance. These cores cannot run continuously. A single core is active at any time, the rest of the cores are inactive and power-gated...

• Type: Conference
• Year: 2010
• Where: CF
• Authors: Pierre Michaud, Yiannakis Sazeides, André Seznec
• Keywords: CF 2010, Cores, On-chip Cores, Sequential Performance