A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips

As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completing designs. In particular, the system interconnect must efficiently service a diverse set of data flows with widely ranging quality-of-service (QoS) requirements. However, the known solutions for off-chip interconnects such as large-scale networks are not necessarily applicable to the on-chip environment. Latency and memory constraints for on-chip interconnects are quite different from largerscale interconnects. This paper introduces a novel on-chip interconnect arbitration scheme. We show how this scheme can be distributed across a chip for high-speed implementation. We compare the performance of the arbitration scheme with other known interconnect arbitration schemes. Existing schemes typically focus heavily on either low latency of service for some initiators, or alternatively on guaranteed bandwidth deliv...

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew Wingard
• Keywords: DATE 2005, Hardware, Interconnect Arbitration Schemes, On-chip Interconnect, On-chip Interconnect Arbitration