A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures

—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the nature of memory system interference is vital to achieve good fairness/complexity/performance trade-offs in CMPs. Our goal in this work is to quantify the latency penalties due to interference in all hardware-controlled, shared units (i.e. the onchip interconnect, shared cache and memory bus). To achieve this, we simulate a wide variety of realistic CMP architectures. In particular, we vary the number of cores, interconnect topology, shared cache size and off-chip memory bandwidth. We observe that interference in the off-chip memory bus accounts for between 63% and 87% of the total interference impact while the impact of cache capacity interference can be lower than indicated by previous studies (between 5% and 32% of the total impact). In addition, as much as 11% of the total impact can be due to uncontrolle...

• Type: Conference
• Year: 2009
• Where: HPCC
• Authors: Magnus Jahre, Marius Grannæs, Lasse Natvig
• Keywords: Destructive Interference, Distributed And Parallel Computing, HPCC 2009, Memory Bus, Total Interference Impact