Re-NUCA: Boosting CMP Performance Through Block Replication

— Chip Multiprocessor (CMP) systems have become the reference architecture for designing micro-processors, thanks to the improvements in semiconductor nanotechnology that have continuously provided a crescent number of faster and smaller per-chip transistors. The interests for CMPs grew up since classical techniques for boosting performance, e.g. the increase of clock frequency and the amount of work performed at each clock cycle, can no longer deliver to significant improvement due to energy constrains and wire delay effects. CMP systems generally adopt a large last-level-cache (LLC) (typically, L2 or L3) shared among all cores, and private L1 caches. As the miss resolution time for private caches depends on the response time of the LLC, which is wire-delay dominated, performance are affected by wire delay. NUCA caches have been proposed for single and multi core systems as a mechanism for tolerating wire-delay effects on the overall performance. In this paper, we introduce a novel ...

• Type: Journal
• Year: 2010
• Where: DSD
• Authors: Pierfrancesco Foglia, Cosimo Antonio Prete, Marco Solinas, Giovanna Monni
• Keywords: Conflict Hit Problem, DSD 2010, Hardware, Performance, Smaller Per-chip Transistors