Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core syst

This paper studies realization and performance comparison of the sequential and weak consistency models in the network-on-chip (NoC) based distributed shared memory (DSM) multi-core systems. Memory consistency constrains the order of shared memory operations for the expected behavior of the multi-core systems. Both the consistency models are realized in the NoC based multi-core systems. The performance of the two consistency models are compared for various sizes of networks using regular mesh topologies and deflection routing algorithm. The results show that the weak consistency improves the performance by 46.17% and 33.76% on average in the code and consistency latencies over the sequential consistency model, due to relaxation in the program order, as the system grows from single core to 64 cores.

• Type: Journal
• Year: 2011
• Where: ASPDAC
• Authors: Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch
• Keywords: ASPDAC 2011, Consistency Models, Hardware, Memory Consistency, Sequential Consistency Model