Reconfigurable Systems Enabled by a Network-on-Chip

A modern SoC design comprises dozens of dedicated IP cores for specialized tasks and processors for generalpurpose tasks. Flexibility is the key feature of processors, since it is easy to modify their tasks behavior at runtime. However, most current SoCs have no capability to modify the hardware behavior or structure after system fabrication. On the other hand, to cope with current SoC internal communication complexity, suggestions to employ Networks on Chip (NoCs) are becoming widespread. This paper proposes to extend the inherent software flexibility to hard IP cores in SoCs using NoCs as the main internal communication resource. This is achieved by making IP cores reconfigurable. The paper advances two main contributions: first, a straightforward design flow for SoCs with reconfigurable IP cores; second, the proposition of a NoC, named Artemis, supporting IP core reconfiguration.

• Type: Conference
• Year: 2006
• Where: FPL
• Authors: Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes
• Keywords: Current Soc, Dedicated Ip Cores, FPL 2006, Hardware, IP Core