Reducing test data volume using external/LBIST hybrid test patterns

A common approachfor large industrial designs is to use logic built-in self-test (LBIST)followed by test data from an external tester. Because the fault coverage with LBIST alone is not suficient, there is a need to top-up the fault coverage with additional deterministic test patterns from an external tester. Thispaper proposes a technique of combining LBIST and deterministic ATPG to form “hybrid test patterns ’’ which merge pseudo-random and deterministic test data. Experiments have been done on the Motorola PowerPCTMmicroprocessor core to study the proposed hybrid test patterns. Hybrid test patterns provide several advantages: I ) can be applied using STUMPS architecture [Bardell 821 with a minor modification, 2) significantly reduce external test data stored in tester memory, 3) reduce the number of pseudorandompattems by orders of magnitude, thus addressing power issues.

• Type: Conference
• Year: 2000
• Where: ITC
• Authors: Debaleena Das, Nur A. Touba
• Keywords: Hardware, Hybrid Test Patterns, ITC 2000, Test Data, Test Patterns