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ITC
2000
IEEE

166views Hardware» more ITC 2000»

A built-in self-repair analyzer (CRESTA) for embedded DRAMs

14 years 3 months ago

Download ic.ncue.edu.tw

Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukas...

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Id	Views	Title	Status

1	166	A built-in self-repair analyzer (CRESTA) for embedded DRAMs	claim
2	124	Wrapper design for embedded core test	claim
3	123	Combinational logic synthesis for diversity in duplex systems	claim
4	110	Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique	claim
5	108	Computer-aided fault to defect mapping (CAFDM) for defect diagnosis	claim
6	104	Application of deterministic logic BIST on industrial circuits	claim
7	101	Deterministic partitioning techniques for fault diagnosis in scan-based BIST	claim
8	101	Reducing test data volume using external/LBIST hybrid test patterns	claim
9	101	Which concurrent error detection scheme to choose ?	claim
10	93	Stuck-fault tests vs. actual defects	claim
11	93	Analysis of interconnect crosstalk defect coverage of test sets	claim
12	91	A mixed mode BIST scheme based on reseeding of folding counters	claim
13	88	Predicting device performance from pass/fail transient signal analysis data	claim
14	84	Non-intrusive BIST for systems-on-a-chip	claim
15	81	A domain coverage metric for the validation of behavioral VHDL descriptions	claim
16	80	A stand-alone integrated test core for time and frequency domain measurements	claim
17	80	Test program synthesis for path delay faults in microprocessor cores	claim
18	79	Analysis of failure sources in surface-micromachined MEMS	claim
19	76	Industrial evaluation of DRAM SIMM tests	claim
20	76	Testing for tunneling opens	claim
21	76	System issues in boundary-scan board test	claim
22	74	A good excuse for reuse: "open" TAP controller design	claim
23	68	Current ratios: a self-scaling technique for production IDDQ testing	claim
24	62	Power conscious test synthesis and scheduling for BIST RTL data paths	claim
25	55	Low power BIST design by hypergraph partitioning: methodology and architectures	claim
26	53	Using on-chip test pattern compression for full scan SoC designs	claim

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