Reduction of detected acceptable faults for yield improvement via error-tolerance

Error-tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on error-rate estimation to support error-tolerance was proposed. Without violating the system error-rate constraint specified by the user, this methodology identifies a set of faults that can be ignored during testing, thereby leading to a significant improvement in yield. However, usually the patterns detecting all of the unacceptable faults also detect a large number of acceptable faults, resulting in a degradation in achievable yield improvement. In this paper, we first provide a probabilistic analysis of this problem and show that a conventional ATPG procedure cannot adequately address this problem. We then present a novel test pattern selection procedure and an output masking technique to deal with this problem. The selection process generates a test set aimed to detect all unacceptable faults but as few acceptable faults as possible. The masking technique then...

• Type: Conference
• Year: 2007
• Where: DATE
• Authors: Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
• Keywords: Acceptable Faults, DATE 2007, Hardware, Unacceptable Faults, Yield Improvement