Redundant wire insertion for yield improvement

Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert redundant wires to construct local cycles and protect the failure of any wire or via for yield improvement. For tested benchmarks, the experimental results show that our proposed insertion approach increases the extra wirelength of internal and external redundant wires by 18.3% and 6.3% to increase the reliability of 56.9% and 5.2% and improve the chip yield by 0.106 and 0.032 on the average in reasonable CPU time, respectively. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids – Placement and routing General Terms: Algorithms, Design

• Type: Conference
• Year: 2009
• Where: GLVLSI
• Authors: Jin-Tai Yan, Zhi-Wei Chen
• Keywords: External Redundant Wires, GLVLSI 2009, Redundant Wires, Two-phase Reliability-driven Insertion, VLSI