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    EURODAC
    1995
    IEEE
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    A reuse scenario for the VHDL-based hardware design flow

    14 years 4 months ago
    A reuse scenario for the VHDL-based hardware design flow
    Download  cadal.cse.nsysu.edu.tw
    Viktor Preis, Renate Henftling, Markus Schütz
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    Added 26 Aug 2010
    Updated 26 Aug 2010
    Type Conference
    Year 1995
    Where EURODAC
    Authors Viktor Preis, Renate Henftling, Markus Schütz, Sabine März-Rössel
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