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GLVLSI
2003
IEEE

RF CMOS circuit optimizing procedure and synthesis tool

14 years 5 months ago
RF CMOS circuit optimizing procedure and synthesis tool
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications described at highabstraction, fabrication dependent technology parameters and un-sized circuit topologies. The output is a sized net list, which meets the user constraints. The synthesis environment considers user-defined performance parameters into account, and it relies on a genetic algorithm based heuristic method to search for a solution in a large design-space. The synthesis tool determines a solution set of design parameters such that the circuit satisfies the overall design constraints. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids – automatic synthesis, simulation. B.7.3 [Integrated Circuits]: Types and Design Styles – standard cells, VLSI. General Terms: Algorithms, Performance, Design.
Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nu
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where GLVLSI
Authors Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nunez
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