DAC
2012
ACM
12 years 2 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
DT
2010
14 years 15 days ago
2010
specified at levels of abstraction higher than the Register Transfer Level (RTL) in hardware description. The essential feature of a behavioral description is that, the designer on...
ICCTA
2007
IEEE
14 years 4 months ago
2007
IEEE
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
LCTRTS
1999
Springer
14 years 4 months ago
1999
Springer
We present a design tool for automated synthesis of embedded systems on distributed COTS-based platforms. Our synthesis tool consists of (1) a graphical user interface for input o...
FCCM
2002
IEEE
14 years 5 months ago
2002
IEEE
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
GLVLSI
2003
IEEE
14 years 5 months ago
2003
IEEE
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications desc...
DATE
2003
IEEE
14 years 5 months ago
2003
IEEE
In this paper, a simulation-based synthesis tool, AMIGO, for analog cell sizing is presented. AMIGO is based upon genetic optimization techniques adapted to circuit sizing. A fram...
ISLPED
2009
ACM
14 years 7 months ago
2009
ACM
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...