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ARCS
1997
Springer

A RISC Processor with Extended Forwarding

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A RISC Processor with Extended Forwarding
The paper examines a simple conceptual modification of the operation unit of a RISC processor. We propose to substitute a part of the conventional general purpose register file by a shift register for all operation results. The presented approach allows to reduce the instruction size for a great deal of instructions and so the instruction stream, and it is also a promising approach to make the processor architecture more regular.
Gert Markwardt, Günter Kemnitz, Rainer G. Spa
Added 07 Aug 2010
Updated 07 Aug 2010
Type Conference
Year 1997
Where ARCS
Authors Gert Markwardt, Günter Kemnitz, Rainer G. Spallek
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