A robust self-resetting CMOS 32-bit parallel adder

This paper presents new circuit configurationsfor a more robust and efficient form of self-resettingCMOS (SRCMOS). Prior structures for SRCMOS have very high performance but are difficult to design and are not robust over process, temperature and voltage variations. The new techniques replace delay chains with logical circuits that will create pulses at the correct times, independent of operational and environmental factors. These concepts are illustrated using a 32-bit parallel adder as a design example.

• Type: Conference
• Year: 2002
• Where: ISCAS
• Authors: Gunok Jung, V. A. Sundarajan, Gerald E. Sobelman
• Keywords: 32-bit Parallel Adder, Hardware, ISCAS 2002, Robust, Techniques Replace Delay