Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

20

FPL
2001
Springer

favoriteEmaildiscussreport

78views Hardware» more FPL 2001»

Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers

14 years 3 months ago

Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers

Download halcyon.usc.edu

Andreas Dandalis, Viktor K. Prasanna, Bharani Thir

Real-time Traffic

FPL 2001 | Hardware |

claim paper

Post Info
More Details (n/a)

Added	28 Jul 2010
Updated	28 Jul 2010
Type	Conference
Year	2001
Where	FPL
Authors	Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam

Comments (0)