Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization

Motivated by the goal of factoring large integers using the Number Field Sieve, several special-purpose hardware designs have been recently proposed for solving large sparse systems of linear equations over finite fields using Wiedemann’s algorithm. However, in the context of factoring large (1024-bit) integers, these proposals were marginally practical due to the complexity of a wafer-scale design, or alternatively the difficulty of connecting smaller chips by a huge number of extremely fast interconnects. In this paper we suggest a new special-purpose hardware device for the (block) Wiedemann algorithm, based on a pipelined systolic architecture reminiscent of the TWIRL device. The new architecture offers simpler chip layout and interconnections, improved efficiency, reduced cost, easy testability and greater flexibility in using the same hardware to solve sparse problems of widely varying sizes and densities. Our analysis indicates that standard fab technologies can be used in...

• Type: Conference
• Year: 2005
• Where: CHES
• Authors: Willi Geiselmann, Adi Shamir, Rainer Steinwandt, Eran Tromer
• Keywords: CHES 2005, Cryptography, Special-purpose Hardware, Special-purpose Hardware Designs, Special-purpose Hardware Device