Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs

We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations arising from Finite Element Method (FEM) applications. The architecture is based on a pipelined linear array of processing elements (PEs). A hardware-oriented matrix “striping” scheme is developed which reduces the number of required processing elements. Our current 8 PE proto

• Type: Conference
• Year: 2006
• Where: FCCM
• Authors: Yousef El-Kurdi, Warren J. Gross, Dennis Giannacopoulos
• Keywords: FCCM 2006, Finite Element Method, FPGA-based Sparse Matrix-vector, Hardware, Processing Elements