Scenario-based Validation of Embedded Systems

This paper describes a scenario-based methodology em-level design validation based on the Abstract State Machines formal method. This scenario-based approach complements an existing model-driven design methodology for embedded systems based on the SystemC UML profile. It allows the designer to functionally validate system components from SystemC UML early at high levels of abstraction and without requiring strong skills and expertise on formal methods. A validation tool integrated into an existing modeldriven co-design environment to support the proposed scenario-based validation flow is also presented.

• Type: Conference
• Year: 2008
• Where: FDL
• Authors: Angelo Gargantini, Elvinia Riccobene, Patrizia Scandurra, Alessandro Carioni
• Keywords: FDL 2008, Natural Language Processing, Scenario-based Approach Complements, Scenario-based Methodology, SystemC UML