A scheduling algorithm for synthesis of bus-partitioned architectures

- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach for integrated scheduling and interconnect binding of bus-segmented data-paths. Experiments show that the approach provides better results than existing methods and is quite flexible.

• Type: Conference
• Year: 1995
• Where: ASPDAC
• Authors: Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru
• Keywords: ASPDAC 1995, Efficient Interconnect Structure, Hardware, Parallelism Bus-partitioned Architectures, Sub-micron Chip Design