Selection of instruction set extensions for an FPGA embedded processor core

A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The instruction set of the PowerPC 405 is extended by selecting additional instructions from the full 32-bit PowerPC instruction set architecture (ISA), of which the PowerPC 405 ISA is a subset. The selected instructions are supported in hardware using the reconfigurable resources of the FPGA. The proposed design process gathers execution statistics for a target application through profiling or simulation. These statistics are then used to estimate the speedup that would be achieved if selected instructions from the full PowerPC ISA are added to the ISA of the PowerPC 405 processor. An experimental study of two embedded benchmarks show significant speedup when this approach is used to extend the PowerPC 405 processor to support various floating-point operations through the use of floating-point cores developed by ...

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: Brian F. Veale, John K. Antonio, Monte P. Tull, S. A. Jones
• Keywords: Distributed And Parallel Computing, Instruction Set, IPPS 2006, Powerpc 405 Isa, PowerPC 405 Processor