Selective Eager Execution on the PolyPath Architecture

Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an execution model to overcome mis-speculation penalties by executing both paths after diffident branches. We present the micro-architecture of the PolyPath processor, which is an extension of an aggressive superscalar, out-of-order architecture. The PolyPath architecture uses a novel instruction tagging and register renaming mechanism to execute instructions from multiple paths simultaneously in the same processor pipeline, while retaining maximum resource availability for single-path code sequences. Results of our execution-driven, pipeline-level simulations show that SEE can improve performance by as much as 36% for the go benchmark, and an average of 14% on SPECint95, when compared to a normal superscalar, out-of-order, speculative execution, monopath processor. Moreover, our architectural model is both eleg...

• Type: Conference
• Year: 1998
• Where: ISCA
• Authors: Artur Klauser, Abhijit Paithankar, Dirk Grunwald
• Keywords: Control-flow Misprediction Penalties, Hardware, ISCA 1998, Selective Eager Execution, Wide-issue Superscalar Processors