ISCA 1998 - PDF Preprint Papers

ISCA 1998 International Symposium on Computer Architecture

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ISCA
1998
IEEE

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A Study of Branch Prediction Strategies

14 years 3 months ago

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In high-performance computer systems, performance losses due to conditional branch instructions can be minimized by predicting a branch outcome and fetching, decoding, and/or issu...

James E. Smith

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Id	Views	Title	Status

1	155	A Study of Branch Prediction Strategies	claim
2	151	Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture	claim
3	151	Alternative Implementations of Two-Level Adaptive Branch Prediction	claim
4	145	Multi-Level Texture Caching for 3D Graphics Hardware	claim
5	144	Declustered Disk Array Architectures with Optimal and Near-Optimal Parallelism	claim
6	143	Lockup-Free Instruction Fetch/Prefetch Cache Organization	claim
7	142	An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work	claim
8	139	Simultaneous Multithreading: Maximizing On-Chip Parallelism	claim
9	137	Accurate Indirect Branch Prediction	claim
10	136	Exploiting Spatial Locality in Data Caches Using Spatial Footprints	claim
11	135	Confidence Estimation for Speculation Control	claim
12	135	Branch Prediction Based on Universal Data Compression Algorithms	claim
13	134	Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor	claim
14	129	Memory System Characterization of Commercial Workloads	claim
15	128	Modeling Program Predictability	claim
16	128	Analytic Evaluation of Shared-memory Systems with ILP Processors	claim
17	126	Switcherland: A QoS Communication Architecture for Workstation Clusters	claim
18	125	Performance Characterization of a Quad Pentium Pro SMP using OLTP Workloads	claim
19	125	Active Pages: A Computation Model for Intelligent Memory	claim
20	124	Threaded Multiple Path Execution	claim
21	123	Weak Ordering - A New Definition	claim
22	123	An Evaluation of Directory Schemes for Cache Coherence	claim
23	122	Design Choices in the SHRIMP System: An Empirical Study	claim
24	122	An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors	claim
25	122	Multiscalar Processors	claim
26	119	Execution Characteristics of Desktop Applications on Windows NT	claim
27	119	Using Prediction to Accelerate Coherence Protocols	claim
28	118	Active Messages: A Mechanism for Integrated Communication and Computation	claim
29	117	Increasing TLB Reach Using Superpages Backed by Shadow Memory	claim
30	115	Improving the Throughput of a Pipeline by Insertion of Delays	claim
31	114	The MIT Alewife Machine: Architecture and Performance	claim
32	114	Tempest and Typhoon: User-Level Shared Memory	claim
33	113	Computer Structures: What Have We Learned from the PDP-11?	claim
34	113	Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors	claim
35	108	Pipeline Gating: Speculation Control for Energy Reduction	claim
36	107	Memory Dependence Prediction Using Store Sets	claim
37	104	Selective Eager Execution on the PolyPath Architecture	claim
38	102	Dynamic History-length Fitting: A Third Level of Adaptivity for Branch Prediction	claim
39	102	The DASH Prototype: Implementation and Performance	claim

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