Selective gate-length biasing for cost-effective runtime leakage control

With process scaling, leakage power reduction has become one of the most important design concerns. Multi-threshold techniques have been used to reduce runtime leakage power without sacrificing performance. In this paper, we propose small biases of transistor gate-length to further minimize power in a manufacturable manner. Unlike multi-Vth techniques, gate-length biasing requires no additional masks and may be performed at any stage in the design process. Our results show that gate-length biasing effectively reduces leakage power by up to 25% with less than 4% delay penalty. We show the feasibility of the technique in terms of manufacturability and pin-compatibility for post-layout power optimization. We also show up to 54% reduction in leakage uncertainty due to inter-die process variation in circuits when biased gate-lengths, versus only unbiased one, are used. Circuits selectively biased show much less sensitivity to both intra and inter die variations. Categories and Subject Desc...

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
• Keywords: DAC 2004, Design Automation, Leakage Power Reduction, Leakage Uncertainty, Runtime Leakage Power