Serial-link bus: a low-power on-chip bus architecture

As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of bus lines of the conventional parallel-line bus CB architecture by multiplexing each m-bits onto a single line. This bus architecture, the serial- link bus SLB, transforms an n-bit conventional parallel-line bus into an n/mline (serial-link) bus. The advantage of serial-link buses is that they have fewer lines, and if the bus width is kept the same, seriallink buses will have larger line width and spacing. Increasing the line width has a twofold reduction effect on the line resistance, as the resistivity of sub-100nm wires significantly drops as the line width increases. Also, increasing the line width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing mopt exists ...

• Type: Conference
• Year: 2005
• Where: ICCAD
• Authors: Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De
• Keywords: Bus Width, Conventional Parallel-line Bus, Hardware, ICCAD 2005, Parallel-line Bus Cb